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All Bit and logical operators working

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This commit is contained in:
Jordi Baylina
2019-12-08 13:39:16 +01:00
parent eaf4396cb3
commit 1f94f7f3ec
12 changed files with 410 additions and 110 deletions
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44
test/basiccases.js
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@@ -202,4 +202,48 @@ describe("basic cases", function () {
]
);
});
it("ops3", async () => {
await doTest(
"ops3.circom",
[
[{in: [-2, 2]}, {neg1: 2,neg2: -2, pow: 4}],
[{in: [0, 1]}, {neg1: 0, neg2: -1, pow: 0}],
[{in: [ 1,-1]}, {neg1: -1, neg2: 1, pow: 1}],
]
);
});
it("Comparation ops", async () => {
await doTest(
"opscmp.circom",
[
[{in: [ 8, 9]}, {lt: 1, leq: 1, eq:0, neq:1, geq: 0, gt:0}],
[{in: [-2,-2]}, {lt: 0, leq: 1, eq:1, neq:0, geq: 1, gt:0}],
[{in: [-1,-2]}, {lt: 0, leq: 0, eq:0, neq:1, geq: 1, gt:1}],
[{in: [ 1,-1]}, {lt: 1, leq: 1, eq:0, neq:1, geq: 0, gt:0}], // In mod, negative values are higher than positive.
]
);
});
it("Bit ops", async () => {
const mask = bigInt("14474011154664524427946373126085988481658748083205070504932198000989141204991");
const m1m = bigInt("7414231717174750794300032619171286606889616317210963838766006185586667290624");
await doTest(
"opsbit.circom",
[
[{in: [ 5, 3]}, {and: 1, or: 7, xor:6, not1:mask.minus(5), shl: 40, shr:0}],
[{in: [ 0, 0]}, {and: 0, or: 0, xor:0, not1:mask, shl: 0, shr:0}],
[{in: [-1, 1]}, {and: 0, or: m1m.add(bigInt.one), xor:m1m.add(bigInt.one), not1:mask.minus(m1m), shl: m1m.shiftLeft(1).and(mask), shr:__P__.shiftRight(1).and(mask)}],
]
);
});
it("Logical ops", async () => {
await doTest(
"opslog.circom",
[
[{in: [ 5, 0]}, {and: 0, or: 1, not1:0}],
[{in: [ 0, 1]}, {and: 0, or: 1, not1:1}],
[{in: [-1, 9]}, {and: 1, or: 1, not1:0}],
[{in: [ 0, 0]}, {and: 0, or: 0, not1:1}],
]
);
});
});

12
test/circuits/ops3.circom Normal file
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@@ -0,0 +1,12 @@
template Ops3() {
signal input in[2];
signal output neg1;
signal output neg2;
signal output pow;
neg1 <-- -in[0];
neg2 <-- -in[1];
pow <-- in[0] ** in[1];
}
component main = Ops3();

18
test/circuits/opsbit.circom Normal file
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@@ -0,0 +1,18 @@
template OpsBit() {
signal input in[2];
signal output and;
signal output or;
signal output xor;
signal output not1;
signal output shl;
signal output shr;
and <-- in[0] & in[1];
or <-- in[0] | in[1];
xor <-- in[0] ^ in[1];
not1 <-- ~in[0];
shl <-- in[0] << in[1];
shr <-- in[0] >> in[1];
}
component main = OpsBit();

18
test/circuits/opscmp.circom Normal file
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@@ -0,0 +1,18 @@
template OpsCmp() {
signal input in[2];
signal output lt;
signal output leq;
signal output eq;
signal output neq;
signal output geq;
signal output gt;
lt <-- in[0] < in[1];
leq <-- in[0] <= in[1];
eq <-- in[0] == in[1];
neq <-- in[0] != in[1];
geq <-- in[0] >= in[1];
gt <-- in[0] > in[1];
}
component main = OpsCmp();

12
test/circuits/opslog.circom Normal file
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@@ -0,0 +1,12 @@
template OpsLog() {
signal input in[2];
signal output and;
signal output or;
signal output not1;
and <-- in[0] && in[1];
or <-- in[0] || in[1];
not1 <-- !in[0];
}
component main = OpsLog();