All Bit and logical operators working

This commit is contained in:
Jordi Baylina
2019-12-08 13:39:16 +01:00
parent eaf4396cb3
commit 1f94f7f3ec
12 changed files with 410 additions and 110 deletions

View File

@@ -0,0 +1,18 @@
template OpsBit() {
signal input in[2];
signal output and;
signal output or;
signal output xor;
signal output not1;
signal output shl;
signal output shr;
and <-- in[0] & in[1];
or <-- in[0] | in[1];
xor <-- in[0] ^ in[1];
not1 <-- ~in[0];
shl <-- in[0] << in[1];
shr <-- in[0] >> in[1];
}
component main = OpsBit();