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All Bit and logical operators working

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This commit is contained in:
Jordi Baylina
2019-12-08 13:39:16 +01:00
parent eaf4396cb3
commit 1f94f7f3ec
12 changed files with 410 additions and 110 deletions
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12
test/circuits/opslog.circom Normal file
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@@ -0,0 +1,12 @@
template OpsLog() {
signal input in[2];
signal output and;
signal output or;
signal output not1;
and <-- in[0] && in[1];
or <-- in[0] || in[1];
not1 <-- !in[0];
}
component main = OpsLog();