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164 lines
7.4 KiB
164 lines
7.4 KiB
/*
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Copyright 2018 0KIMS association.
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This file is part of circom (Zero Knowledge Circuit Compiler).
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circom is a free software: you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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circom is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with circom. If not, see <https://www.gnu.org/licenses/>.
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*/
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/***************************************************************************************************
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Each level on a SMTProcessor has a state.
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The state of the level depends on the state of te botom level and on `xor` and
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`is0` signals.
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`isOldLev` 1 when is the level where oldLeaf is.
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`xor` signal is 0 if the index bit at the current level is the same in the old
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and the new index, and 1 if it is different.
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`is0` signal, is 1 if we are inserting/deleting in an empty leaf and 0 if we
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are inserting/deleting in a leaf that contains an element.
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The states are:
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top: While the index bits of the old and new insex in the top level is the same, whe are in the top state.
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old0: When the we reach insert level, we go to old0 state
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if `is0`=1.
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btn: Once in insert level and `is0` =0 we go to btn or new1 level if xor=1
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new1: This level is reached when xor=1. Here is where we insert/delete the hash of the
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old and the new trees with just one element.
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na: Not appliable. After processing it, we go to the na level.
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Fnction
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fnc[0] fnc[1]
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0 0 NOP
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0 1 UPDATE
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1 0 INSERT
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1 1 DELETE
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###########
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# #
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┌────────────────────────────▶# upd #─────────────────────┐
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│ ## ## │
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│ ######### │
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levIns=1 │ │
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fnc[0]=0 │ │ any
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│ │
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│ │
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│ │
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│ ########### │
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│ levIns=1 # # │
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levIns=0 │ is0=1 ┌────────────▶# old0 #────────┐ │ any
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┌─────┐ │ fnc[0]=1│ ## ## │ │ ┌──────┐
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│ │ │ │ ######### │ any │ │ │
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│ ▼ │ │ │ ▼ ▼ │
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│ ########### │ │ ########### │
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│ # # ────────────┘ └────────▶# #│
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└──# top # # na #
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## ## ───────────────────┐ levIns=1 ┌──▶## ##
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######### │ is0=0 │ #########
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│ │ fnc[0]=1 │
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│ │ xor=1 ########### │ any
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│ └──────────────────▶# # │
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│ # new1 #──┘
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│ ## ##
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└────────────────────────────────┐ #########
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levIns=1 │ ▲
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is0=0 │ ┌─────┘
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fnc[0]=1 │ ###########│ xor=1
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xor=0 │ # #
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▼# btn #
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## ##
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#########◀───────┐
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│ │
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│ │
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└────────────┘
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xor=0
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***************************************************************************************************/
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template SMTProcessorSM() {
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signal input xor;
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signal input is0;
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signal input levIns;
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signal input fnc[2];
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signal input prev_top;
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signal input prev_old0;
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signal input prev_bot;
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signal input prev_new1;
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signal input prev_na;
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signal input prev_upd;
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signal output st_top;
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signal output st_old0;
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signal output st_bot;
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signal output st_new1;
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signal output st_na;
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signal output st_upd;
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signal aux1;
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signal aux2;
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aux1 <== prev_top * levIns;
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aux2 <== aux1*fnc[0]; // prev_top * levIns * fnc[0]
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// st_top = prev_top*(1-levIns)
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// = + prev_top
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// - prev_top * levIns = aux1
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st_top <== prev_top - aux1;
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// st_old0 = prev_top * levIns * is0 * fnc[0]
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// = + prev_top * levIns * is0 * fnc[0] = aux2 * is0
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st_old0 <== aux2 * is0; // prev_top * levIns * is0 * fnc[0]
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// st_new1 = prev_top * levIns * (1-is0)*fnc[0] * xor + prev_bot*xor =
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// = + prev_top * levIns * fnc[0] * xor = aux2 * xor
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// - prev_top * levIns * is0 * fnc[0] * xor = st_old0 * xor
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// + prev_bot * xor = prev_bot * xor
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st_new1 <== (aux2 - st_old0 + prev_bot)*xor;
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// st_bot = prev_top * levIns * (1-is0)*fnc[0] * (1-xor) + prev_bot*(1-xor);
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// = + prev_top * levIns * fnc[0]
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// - prev_top * levIns * is0 * fnc[0]
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// - prev_top * levIns * fnc[0] * xor
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// + prev_top * levIns * is0 * fnc[0] * xor
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// + prev_bot
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// - prev_bot * xor
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st_bot <== (1-xor) * (aux2 - st_old0 + prev_bot)
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// st_upd = prev_top * (1-fnc[0]) *levIns;
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// = + prev_top * levIns
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// - prev_top * levIns * fnc[0]
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st_upd <== aux1 - aux2
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// st_na = prev_new1 + prev_old0 + prev_na + prev_upd;
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// = + prev_new1
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// + prev_old0
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// + prev_na
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// + prev_upd
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st_na <== prev_new1 + prev_old0 + prev_na + prev_upd;
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}
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