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Add Hardware Abstraction Layer (#56)
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1
backend/src/hal/tests/mod.rs
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1
backend/src/hal/tests/mod.rs
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pub mod vec_znx;
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120
backend/src/hal/tests/vec_znx/generics.rs
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120
backend/src/hal/tests/vec_znx/generics.rs
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use itertools::izip;
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use sampling::source::Source;
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use crate::hal::{
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api::{
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VecZnxAddNormal, VecZnxAlloc, VecZnxDecodeVeci64, VecZnxEncodeVeci64, VecZnxFillUniform, VecZnxStd, ZnxInfos, ZnxView,
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ZnxViewMut,
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},
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layouts::{Backend, Module, VecZnx},
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};
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pub fn test_vec_znx_fill_uniform<B: Backend>(module: &Module<B>)
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where
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Module<B>: VecZnxFillUniform + VecZnxStd + VecZnxAlloc,
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{
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let basek: usize = 17;
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let size: usize = 5;
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let mut source: Source = Source::new([0u8; 32]);
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let cols: usize = 2;
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let zero: Vec<i64> = vec![0; module.n()];
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let one_12_sqrt: f64 = 0.28867513459481287;
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(0..cols).for_each(|col_i| {
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let mut a: VecZnx<_> = module.vec_znx_alloc(cols, size);
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module.vec_znx_fill_uniform(basek, &mut a, col_i, size * basek, &mut source);
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(0..cols).for_each(|col_j| {
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if col_j != col_i {
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(0..size).for_each(|limb_i| {
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assert_eq!(a.at(col_j, limb_i), zero);
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})
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} else {
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let std: f64 = module.vec_znx_std(basek, &a, col_i);
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assert!(
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(std - one_12_sqrt).abs() < 0.01,
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"std={} ~!= {}",
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std,
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one_12_sqrt
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);
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}
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})
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});
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}
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pub fn test_vec_znx_add_normal<B: Backend>(module: &Module<B>)
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where
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Module<B>: VecZnxAddNormal + VecZnxStd + VecZnxAlloc,
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{
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let basek: usize = 17;
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let k: usize = 2 * 17;
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let size: usize = 5;
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let sigma: f64 = 3.2;
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let bound: f64 = 6.0 * sigma;
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let mut source: Source = Source::new([0u8; 32]);
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let cols: usize = 2;
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let zero: Vec<i64> = vec![0; module.n()];
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let k_f64: f64 = (1u64 << k as u64) as f64;
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(0..cols).for_each(|col_i| {
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let mut a: VecZnx<_> = module.vec_znx_alloc(cols, size);
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module.vec_znx_add_normal(basek, &mut a, col_i, k, &mut source, sigma, bound);
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(0..cols).for_each(|col_j| {
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if col_j != col_i {
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(0..size).for_each(|limb_i| {
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assert_eq!(a.at(col_j, limb_i), zero);
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})
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} else {
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let std: f64 = module.vec_znx_std(basek, &a, col_i) * k_f64;
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assert!((std - sigma).abs() < 0.1, "std={} ~!= {}", std, sigma);
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}
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})
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});
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}
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pub fn test_vec_znx_encode_vec_i64_lo_norm<B: Backend>(module: &Module<B>)
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where
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Module<B>: VecZnxEncodeVeci64 + VecZnxDecodeVeci64 + VecZnxAlloc,
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{
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let basek: usize = 17;
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let size: usize = 5;
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let k: usize = size * basek - 5;
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let mut a: VecZnx<_> = module.vec_znx_alloc(2, size);
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let mut source: Source = Source::new([0u8; 32]);
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let raw: &mut [i64] = a.raw_mut();
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raw.iter_mut().enumerate().for_each(|(i, x)| *x = i as i64);
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(0..a.cols()).for_each(|col_i| {
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let mut have: Vec<i64> = vec![i64::default(); module.n()];
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have.iter_mut()
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.for_each(|x| *x = (source.next_i64() << 56) >> 56);
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module.encode_vec_i64(basek, &mut a, col_i, k, &have, 10);
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let mut want: Vec<i64> = vec![i64::default(); module.n()];
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module.decode_vec_i64(basek, &a, col_i, k, &mut want);
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izip!(want, have).for_each(|(a, b)| assert_eq!(a, b, "{} != {}", a, b));
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});
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}
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pub fn test_vec_znx_encode_vec_i64_hi_norm<B: Backend>(module: &Module<B>)
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where
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Module<B>: VecZnxEncodeVeci64 + VecZnxDecodeVeci64 + VecZnxAlloc,
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{
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let basek: usize = 17;
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let size: usize = 5;
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for k in [1, basek / 2, size * basek - 5] {
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let mut a: VecZnx<_> = module.vec_znx_alloc(2, size);
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let mut source = Source::new([0u8; 32]);
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let raw: &mut [i64] = a.raw_mut();
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raw.iter_mut().enumerate().for_each(|(i, x)| *x = i as i64);
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(0..a.cols()).for_each(|col_i| {
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let mut have: Vec<i64> = vec![i64::default(); module.n()];
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have.iter_mut().for_each(|x| {
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if k < 64 {
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*x = source.next_u64n(1 << k, (1 << k) - 1) as i64;
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} else {
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*x = source.next_i64();
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}
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});
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module.encode_vec_i64(basek, &mut a, col_i, k, &have, 63);
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let mut want: Vec<i64> = vec![i64::default(); module.n()];
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module.decode_vec_i64(basek, &a, col_i, k, &mut want);
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izip!(want, have).for_each(|(a, b)| assert_eq!(a, b, "{} != {}", a, b));
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})
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}
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}
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2
backend/src/hal/tests/vec_znx/mod.rs
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2
backend/src/hal/tests/vec_znx/mod.rs
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@@ -0,0 +1,2 @@
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mod generics;
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pub use generics::*;
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