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Add Hardware Abstraction Layer (#56)

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This commit is contained in:
Jean-Philippe Bossuat
2025-08-08 19:22:42 +02:00
committed by GitHub
parent 833520b163
commit 0e0745065e
194 changed files with 17397 additions and 11955 deletions
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16
core/src/elem.rs
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@@ -1,6 +1,4 @@
use backend::{Backend, Module, ZnxInfos};
use crate::FourierGLWECiphertext;
use backend::hal::api::ZnxInfos;
pub trait Infos {
type Inner: ZnxInfos;
@@ -54,15 +52,3 @@ pub trait SetMetaData {
fn set_basek(&mut self, basek: usize);
fn set_k(&mut self, k: usize);
}
pub trait GetRow<B: Backend> {
fn get_row<R>(&self, module: &Module<B>, row_i: usize, col_j: usize, res: &mut FourierGLWECiphertext<R, B>)
where
R: AsMut<[u8]> + AsRef<[u8]>;
}
pub trait SetRow<B: Backend> {
fn set_row<R>(&mut self, module: &Module<B>, row_i: usize, col_j: usize, a: &FourierGLWECiphertext<R, B>)
where
R: AsRef<[u8]>;
}