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Add BDD Arithmetic (#98)
* Added some circuit, evaluation + some layouts * Refactor + memory reduction * Rows -> Dnum, Digits -> Dsize * fix #96 + glwe_packing (indirectly CBT) * clippy
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Jean-Philippe Bossuat
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GitHub
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commit
6357a05509
220
poulpy-schemes/src/tfhe/bdd_arithmetic/bdd_2w_to_1w.rs
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220
poulpy-schemes/src/tfhe/bdd_arithmetic/bdd_2w_to_1w.rs
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@@ -0,0 +1,220 @@
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use itertools::Itertools;
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use poulpy_core::layouts::prepared::GGSWCiphertextPreparedToRef;
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use poulpy_hal::layouts::{Backend, DataMut, DataRef, Module, Scratch};
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use crate::tfhe::bdd_arithmetic::{
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BitCircuitInfo, Circuit, CircuitExecute, FheUintBlocks, FheUintBlocksPrep, UnsignedInteger, circuits,
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};
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/// Operations Z x Z -> Z
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pub(crate) struct Circuits2WTo1W<C: BitCircuitInfo + 'static, const WORD_SIZE: usize>(pub &'static Circuit<C, WORD_SIZE>);
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pub trait EvalBDD2WTo1W<BE: Backend, T: UnsignedInteger> {
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fn eval_bdd_2w_to_1w<R, A, B>(
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&self,
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module: &Module<BE>,
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out: &mut FheUintBlocks<R, T>,
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a: &FheUintBlocksPrep<A, BE, T>,
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b: &FheUintBlocksPrep<B, BE, T>,
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scratch: &mut Scratch<BE>,
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) where
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R: DataMut,
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A: DataRef,
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B: DataRef;
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}
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impl<C: BitCircuitInfo + 'static, const WORD_SIZE: usize, BE: Backend, T: UnsignedInteger> EvalBDD2WTo1W<BE, T>
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for Circuits2WTo1W<C, WORD_SIZE>
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where
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Circuit<C, WORD_SIZE>: CircuitExecute<BE, T>,
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{
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fn eval_bdd_2w_to_1w<R, A, B>(
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&self,
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module: &Module<BE>,
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out: &mut FheUintBlocks<R, T>,
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a: &FheUintBlocksPrep<A, BE, T>,
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b: &FheUintBlocksPrep<B, BE, T>,
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scratch: &mut Scratch<BE>,
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) where
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R: DataMut,
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A: DataRef,
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B: DataRef,
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{
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eval_bdd_2w_to_1w(module, self.0, out, a, b, scratch);
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}
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}
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pub fn eval_bdd_2w_to_1w<R: DataMut, A: DataRef, B: DataRef, T: UnsignedInteger, C: CircuitExecute<BE, T>, BE: Backend>(
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module: &Module<BE>,
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circuit: &C,
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out: &mut FheUintBlocks<R, T>,
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a: &FheUintBlocksPrep<A, BE, T>,
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b: &FheUintBlocksPrep<B, BE, T>,
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scratch: &mut Scratch<BE>,
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) {
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#[cfg(debug_assertions)]
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{
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assert_eq!(out.blocks.len(), T::WORD_SIZE);
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assert_eq!(b.blocks.len(), T::WORD_SIZE);
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assert_eq!(b.blocks.len(), T::WORD_SIZE);
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}
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// Collects inputs into a single array
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let inputs: Vec<&dyn GGSWCiphertextPreparedToRef<BE>> = a
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.blocks
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.iter()
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.map(|x| x as &dyn GGSWCiphertextPreparedToRef<BE>)
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.chain(
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b.blocks
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.iter()
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.map(|x| x as &dyn GGSWCiphertextPreparedToRef<BE>),
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)
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.collect_vec();
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// Evaluates out[i] = circuit[i](a, b)
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circuit.execute(module, &mut out.blocks, &inputs, scratch);
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}
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#[macro_export]
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macro_rules! define_bdd_2w_to_1w_trait {
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($(#[$meta:meta])* $vis:vis $trait_name:ident, $method_name:ident) => {
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$(#[$meta])*
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$vis trait $trait_name<T: UnsignedInteger, BE: Backend> {
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fn $method_name<A, B>(
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&mut self,
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module: &Module<BE>,
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a: &FheUintBlocksPrep<A, BE, T>,
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b: &FheUintBlocksPrep<B, BE, T>,
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scratch: &mut Scratch<BE>,
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) where
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A: DataRef,
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B: DataRef;
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}
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};
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}
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#[macro_export]
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macro_rules! impl_bdd_2w_to_1w_trait {
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($trait_name:ident, $method_name:ident, $ty:ty, $n:literal, $circuit_ty:ty, $output_circuits:path) => {
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impl<D: DataMut, BE: Backend> $trait_name<$ty, BE> for FheUintBlocks<D, $ty>
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where
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Circuits2WTo1W<$circuit_ty, $n>: EvalBDD2WTo1W<BE, $ty>,
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{
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fn $method_name<A, B>(
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&mut self,
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module: &Module<BE>,
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a: &FheUintBlocksPrep<A, BE, $ty>,
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b: &FheUintBlocksPrep<B, BE, $ty>,
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scratch: &mut Scratch<BE>,
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) where
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A: DataRef,
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B: DataRef,
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{
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const OP: Circuits2WTo1W<$circuit_ty, $n> = Circuits2WTo1W::<$circuit_ty, $n>(&$output_circuits);
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OP.eval_bdd_2w_to_1w(module, self, a, b, scratch);
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}
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}
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};
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}
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define_bdd_2w_to_1w_trait!(pub Add, add);
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define_bdd_2w_to_1w_trait!(pub Sub, sub);
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define_bdd_2w_to_1w_trait!(pub Sll, sll);
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define_bdd_2w_to_1w_trait!(pub Sra, sra);
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define_bdd_2w_to_1w_trait!(pub Srl, srl);
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define_bdd_2w_to_1w_trait!(pub Slt, slt);
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define_bdd_2w_to_1w_trait!(pub Sltu, sltu);
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define_bdd_2w_to_1w_trait!(pub Or, or);
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define_bdd_2w_to_1w_trait!(pub And, and);
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define_bdd_2w_to_1w_trait!(pub Xor, xor);
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impl_bdd_2w_to_1w_trait!(
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Add,
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add,
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u32,
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32,
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circuits::u32::add_codegen::AnyBitCircuit,
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circuits::u32::add_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Sub,
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sub,
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u32,
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32,
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circuits::u32::sub_codegen::AnyBitCircuit,
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circuits::u32::sub_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Sll,
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sll,
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u32,
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32,
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circuits::u32::sll_codegen::AnyBitCircuit,
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circuits::u32::sll_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Sra,
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sra,
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u32,
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32,
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circuits::u32::sra_codegen::AnyBitCircuit,
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circuits::u32::sra_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Srl,
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srl,
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u32,
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32,
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circuits::u32::srl_codegen::AnyBitCircuit,
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circuits::u32::srl_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Slt,
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slt,
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u32,
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1,
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circuits::u32::slt_codegen::AnyBitCircuit,
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circuits::u32::slt_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Sltu,
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sltu,
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u32,
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1,
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circuits::u32::sltu_codegen::AnyBitCircuit,
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circuits::u32::sltu_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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And,
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and,
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u32,
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32,
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circuits::u32::and_codegen::AnyBitCircuit,
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circuits::u32::and_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Or,
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or,
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u32,
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1,
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circuits::u32::or_codegen::AnyBitCircuit,
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circuits::u32::or_codegen::OUTPUT_CIRCUITS
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);
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impl_bdd_2w_to_1w_trait!(
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Xor,
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xor,
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u32,
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1,
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circuits::u32::xor_codegen::AnyBitCircuit,
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circuits::u32::xor_codegen::OUTPUT_CIRCUITS
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);
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