Add bdd rotation

This commit is contained in:
Jean-Philippe Bossuat
2025-10-24 18:13:43 +02:00
parent 96d8f4cfc4
commit d989867c91
13 changed files with 177 additions and 32 deletions

View File

@@ -39,6 +39,17 @@ impl<D: DataRef, T: UnsignedInteger> GLWEInfos for FheUintBlocks<D, T> {
}
}
impl<D: Data, T: UnsignedInteger> FheUintBlocks<D, T> {
pub fn new(blocks: Vec<GLWE<D>>) -> Self {
assert_eq!(blocks.len(), T::WORD_SIZE);
Self {
blocks,
_base: 1,
_phantom: PhantomData,
}
}
}
impl<T: UnsignedInteger> FheUintBlocks<Vec<u8>, T> {
pub fn alloc_from_infos<A, BE: Backend>(module: &Module<BE>, infos: &A) -> Self
where

View File

@@ -3,6 +3,7 @@ use std::marker::PhantomData;
use poulpy_core::layouts::{
Base2K, Dnum, Dsize, GGSWInfos, GGSWPreparedFactory, GLWEInfos, LWEInfos, Rank, TorusPrecision, prepared::GGSWPrepared,
};
use poulpy_core::layouts::{GGSWPreparedToMut, GGSWPreparedToRef};
use poulpy_core::{GGSWEncryptSk, ScratchTakeCore, layouts::GLWESecretPreparedToRef};
use poulpy_hal::layouts::{Backend, Data, DataRef, Module};
@@ -28,6 +29,28 @@ impl<T: UnsignedInteger, BE: Backend> FheUintBlocksPreparedFactory<T, BE> for Mo
{
}
pub trait GetGGSWBit<T: UnsignedInteger, BE: Backend> {
fn get_bit(&self, bit: usize) -> GGSWPrepared<&[u8], BE>;
}
impl<D: DataRef, T: UnsignedInteger, BE: Backend> GetGGSWBit<T, BE> for FheUintBlocksPrepared<D, T, BE> {
fn get_bit(&self, bit: usize) -> GGSWPrepared<&[u8], BE> {
assert!(bit <= self.blocks.len());
self.blocks[bit].to_ref()
}
}
pub trait GetGGSWBitMut<T: UnsignedInteger, BE: Backend> {
fn get_bit(&mut self, bit: usize) -> GGSWPrepared<&mut [u8], BE>;
}
impl<D: DataMut, T: UnsignedInteger, BE: Backend> GetGGSWBitMut<T, BE> for FheUintBlocksPrepared<D, T, BE> {
fn get_bit(&mut self, bit: usize) -> GGSWPrepared<&mut [u8], BE> {
assert!(bit <= self.blocks.len());
self.blocks[bit].to_mut()
}
}
pub trait FheUintBlocksPreparedFactory<T: UnsignedInteger, BE: Backend>
where
Self: Sized + GGSWPreparedFactory<BE>,