rv32-rs

RISC-V (RV32I variant, with some of the M extension) implementation by hand to get familiar with Risc-V’s internals. Do not use, for learning purposes only.

Follows the specification from: - https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html - https://five-embeddev.github.io/riscv-docs-html/riscv-user-isa-manual/latest-adoc/rv-32-64g.html